The present invention relates to semiconductor devices and methods of manufacturing semiconductor devices. The present invention has particular applicability to double-gate devices.
The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths, below 100 nanometers (nm), high reliability and increased manufacturing throughput. The reduction of design features below 100 nm challenges the limitations of conventional methodology.
For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 100 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are therefore being explored to improve FET performance and allow further device scaling:
Double-gate MOSFETs represent new structures that have been considered as candidates for succeeding existing planar MOSFETs. In several respects, the double-gate MOSFETs offer better characteristics than the conventional bulk silicon MOSFETs. These improvements arise because the double-gate MOSFET has a gate electrode on both sides of the channel, rather than only on one side as in conventional MOSFETs. When there are two gates, the electric field generated by the drain is better screened from the source end of the channel. Also, two gates can control roughly twice as much current as a single gate, resulting in a stronger switching signal.
A FinFET is a recent double-gate structure that exhibits good short channel behavior. A FinFET includes a channel formed in a vertical fin. The FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.
Implementations consistent with the present invention provide a double-gate MOSFET having a dual polysilicon layer over the gate area that is used to enhance chemical mechanical polishing (CMP) planarization of the polysilicon.
One implementation consistent with the invention provides a method of manufacturing a semiconductor device. The method includes forming a fin structure on an insulator and forming a gate structure over at least a portion of the fin structure and a portion of the insulator. The gate structure includes a first layer and a second layer formed over the first layer. The method further includes planarizing the gate structure by performing a chemical-mechanical polishing (CMP) of the gate structure. The planarization rate of the first layer of the gate structure may be slower than that of the second layer of the gate structure. The planarization continues until the first layer is exposed in an area over the fin.
An alternate implementation consistent with the invention is directed to a semiconductor device. The device includes a fin structure formed over an insulator. The fin structure includes first and second ends. At least a portion of the fin structure acts as a channel in the semiconductor device. An amorphous silicon layer is formed over at least a portion of the fin structure. A polysilicon layer is formed around at least the portion of the amorphous silicon layer. The amorphous silicon layer protrudes through the polysilicon layer in an area over the fin structure. A source region is connected to the first end of the fin structure. A drain region is connected to the second end of the fin structure.